The present invention relates to the field of electrical integrated circuit testing. More particularly, the present invention relates to a system and method to reduce scan test pins on an integrated circuit.
Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems include processors that have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, electronic systems designed to provide these results include a variety of components including microelectronic integrated circuits. Efficient and reliable performance testing of integrated circuit (IC) chips is critical to assure the IC operates properly.
The complexity of commonly used integrated circuits has advanced dramatically and built in self test (BIST) diagnostics capability is essential for effective circuit testing, debugging, and maintenance. Modern BIST techniques typically include the insertion of a scan test architecture in an IC to provide controllability and observability of IC components. Scan testing of complex electronic systems and circuits often requires analysis of measurement points (e.g., appropriately selected circuit nodes) by applying test vectors to stimulate certain aspects (e.g., a functional logic component) of a circuit. For example, microelectronic chips typically have numerous connections between functional logic components in addition to exterior devices and these connections are often appropriate circuit nodes for testing fault isolation and detection.
As a general proposition, information gathered at test measurement points such as circuit nodes are communicated to exterior devices for analysis. Typically scan architectures require additional separate exterior pins dedicated to communicate signals associated with scan testing to devices not on the chip. For example, an International Electrical and Electronic Engineering (IEEE) Standard 1149.1 boundary scan compliant architecture (also referred to as Joint Test Action Group (JTAG)) requires at least 4 pins dedicated to communicate signals associated with scan operations. The IEEE 1149.1 pins are Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK) and Test Mode Select (TMS). Typically, a full scan architecture requires a minimum set of 5 exterior pins per each scan chain. The 5 pins are dedicated to communications associated with full scan operations. The typical minimum full scan pins are scan enable, scan test mode, scan input, scan output and scan test clock.
FIG. 1 is a block diagram example of a prior art boundary and full scan IC architecture 100. Prior art scan architecture 100 comprises normal operation pins 111 through 116, boundary scan cells 121 through 126, functional logic components 131 through 133, full scan chains 141 through 143, full scan test mode (STM) pins 151, 161 and 171, full scan enable (SE) pins 152, 162 and 172, full scan test clock (STC) pins 153, 163, and 173, full scan input (SI) pins 154, 164 and 174, full scan output (SO) pins 155, 165 and 175, boundary scan test data input (TDI) pin 183, boundary scan test mode select (TMS) pin 181, boundary scan test clock (TCK) pin 182 and boundary scan test data output (TDO) pin 184, standard IEEE 1149.1 boundary scan TAP controller 191, instruction register 195, MUX 197 and MUX 198. Normal operation pins 111 through 116 and functional logic components 131 through 133 facilitate normal operations. The remaining listed components of full scan IC architecture 100 facilitate scan mode operations. Each of the full scan chains 141 though 143 and boundary scan cells 121 through 126 require dedicated individual sets of scan operation signals transmitted on separate exterior pins. Each set of pins dedicated to scan operation signals includes a pin for a STM signal, a pin for a SE signal, a pin for a STC signal, a pin for a SI signal, and pin for a SO signal.
Usually the requirement that each scan chain has an individual sets of scan operation signals results in numerous pins being dedicated to scan testing operations. Full scan test mode (STM) pins 151, 161 and 171 are required for the communication of test mode control signals. Full scan enable (SE) pins 152, 162 and 172 are required for the communication of an enable scan signal that controls scan shifting between full scan cells in a scan chain and information loading from functional logic into a scan chain. Full scan test clocks (STC) pins 153, 163, and 173 are required for the transmission of clock signals to components included in a scan chain. Full scan input (SI) pins 154, 164 and 174 are required to provide a path for data signals (e.g., test vectors, instructions, etc.) to a scan chain from exterior devices. Full scan output (SO) pins 155, 165 and 175 are required to transmitted full scan test results to exterior devices. Boundary scan test data input (TDI) pin 181 only inputs information associated with boundary scan operations. Boundary scan test mode select (TMS) pin 181 is only utilized to select a boundary test mode. Boundary scan test clock (TCK) pin 182 is only utilized to generate a boundary scan clock signal. Boundary scan test data output (TDO) pin 183 is only utilized to communicate boundary scan output information to exterior devices.
Usually a complex IC requires a large number of dedicated scan testing pins to accommodate the numerous scan chains included in typical ICs. Although it is important to test an IC, providing dedicated input and output (IO) pins for scan testing operations takes up precious chip space and expends valuable placement resources. Thus, a chip designer often has to expend significant chip resources for scan testing or leave out advantageous scan testing features.
What is required is a system and method that permits appropriate scan testing of internal components while reducing the number of external pins required to perform the scan testing. The system and method should permit a designer to efficiently and effectively scan test integrated circuit components while decreasing the number of external pins dedicated to scan operations. The electronic system and method should minimize adverse redesign impacts to existing IC designs and facilitate utilization of existing testing scan architectures.
The present invention is a system and method that permits appropriate scan testing of internal components while reducing the number of external pins required to perform the scan testing. The system and method facilitates efficient and effective scan testing of integrated circuit components while decreasing the number of external pins dedicated to scan operations. The electronic system and method also minimizes adverse redesign impacts to existing IC designs and facilitates utilization of existing scan testing architectures.
In one embodiment of the present invention, reduced pin full scan integrated circuit (IC) testing system and method utilizes standard IEEE 1149.1 pins (e.g. TDO, TDI, TMS, TCK, etc.) to perform both boundary scan and full scan testing. A TAP controller generates signals to control both the boundary scan and full scan operations. For example, a full scan cell facilitates full scan capture and shift operations when the TAP controller issues an active full scan test mode signal and an active full scan enable signal (e.g., during shifting). In one embodiment of the present invention the scan test mode signal is a static signal that is programmed by the TAP controller. In one example of a reduced pin scan system, a scan enable signal is asserted when a TAP controller is in a shift state and the TAP controller""s instruction register is loaded with a test mode instruction. A functional clock capture cycle is applied when the state machine of the TAP controller is in run/idle state. A TDI pin and TDO pin are utilized to facilitate boundary scan input, boundary scan output, full scan input and full scan output requirements respectively.